SH7041A datasheet(16/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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16 / 923 page

Section

Page

Description

25.4 A/D Converter

Characteristics

Table 25.16 A/D

Converter Timing (A

mask)

779

Table amended

Non-linearity error

Offset error*

Full scale error*

Quantize error*

26.2 DC

Characteristics

Table 26.2 DC

Characteristics

782

Table amended

Schmitt

trigger input

voltage

PA2, PA5, PA6–

PA9,

PE0–PE15

+ – V

–

CC×

0.07

——

≥ V

CC× 0.9V (min)

–

≤ V

CC× 0.2V (max)

783

Table amended

Analog

supply

—

f = 16.7MHz

current

ref

—

0.5

QFP144 version only

*3 2 mA in the A mask version of MASK products.

26.3.2 Control

Signal Timing

Table 26.5 Control

Signal Timing

786

Note amended

Notes: *1 SH7042/43 ZTAT (excluding A mask) are 3.2V.

*2 The

RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals

are asynchronous inputs, but when the setup times

shown here are provided, the signals are considered to

have produced changes at clock rise (for

RES, MRES,

BREQ) or clock fall (for NMI and IRQ7–IRQ0). If the

setup times are not provided, recognition is delayed until

the next clock rise or fall.

26.3.3 Bus Timing

Figure 26.12 DRAM

Cycle (Normal Mode,

1 Wait, TPC = 0,

RCD = 0)

795

Figure amended

Tcw1

Tc2

CASD1

CAC

RAC

RDS

Column address

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