SH7041A datasheet(8/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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8 / 923 page

Section

Page

Description

11.2.3 DMA

Transfer Count

Registers 0–3

(DMATCR0–

DMATCR3)

220

Description amended

The data for the upper 8 bits of a DMATCR is 0

when read.

11.2.4 DMA

Channel Control

Registers 0–3

(CHCR0–CHCR3)

221

Description amended

• Bits 31–21—Reserved bits: Data are 0

when read. The write

value always be 0.

224

Description amended

• Bit 7—Reserved bits: Data is 0

when read. The write value

always be 0.

11.2.5 DMAC

Operation Register

(DMAOR)

226

Description amended

• Bits 15–10—Reserved bits: Data are 0

when read. The write

value always be 0.

227

Description amended

• Bits 7–3—Reserved bits: Data are 0

when read. The write

value always be 0.

11.3.3 Channel

Priority

Figure 11.3 Round

Robin Mode

233

Figure amended

Channel 0 is given the lowest

priority.

12.4.5 Cascade

Connection Mode

Figure 12.23

Cascade Connection

Operation Example

(Phase Counting

Mode)

337

Figure amended

TCLKC

TCLKD

12.4.9

Complementary

PWM Mode

Figure 12.55

Example of Output

Phase Switching by

External Input (1)

373

Figure amended

When BDC = 1, N = 0, P = 0, FB = 0, output active level = high

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