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SH7041A 数据表(PDF) 18 Page - Renesas Technology Corp |
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SH7041A 数据表(HTML) 18 Page - Renesas Technology Corp |
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18 / 923 page ![]() Section Page Description Appendix B Block Diagrams Figure B.19 PB4/ IRQ2/POE2/ CASH,PB3/IRQ1/ POE1/CASL Block Diagram (F-ZTAT Version) 844 Note added A17 Note: * Only when n = 4. On-chip flash memory* Appendix C Pin States Table C.1 Pin Modes During Reset, Power-Down, and Bus Right Release Modes (144 Pin) 865 Table amended Pin modes Pin Function Reset Power-Down Bus Right Standby in Bus Class Pin Name Power-OnManual Standby Sleep Release Right Release Clock CK O O H* 1 OO O System RES II I I I I control MRES Z* 4 IZ I I Z WDTOVF O* 3 O* 3 OO O O BREQ Z* 4 IZ I I I BACK Z* 4 OZ O L L Interrupt NMI I I I I I I IRQ0–IRQ7 Z* 4 IZ I I Z IRQOUT (PD30) Z* 4 OH* 1 HO H* 1 IRQOUT (PE15) Z* 4 OZ H O Z Address bus A0–A21 O* 2 OZ O Z Z Data bus D0–D31 Z* 4 I/O Z I/O Z Z Bus WAIT Z* 4 IZ I Z Z control RD/WR, RAS Z* 4 OO O Z Z CASH, CASL, CASLH, CASLL Z* 4 OO O Z Z RD HO Z O Z Z CS0, CS1 HO Z O Z Z CS2, CS3 Z* 4 OZ O Z Z WRHH, WRHL, WRH, WRL HO Z O Z Z AH Z* 4 OZ O Z Z DMAC DACK0, DACK1 (PD26, PD27) Z* 4 OO* 1 OO O* 1 DACK0, DACK1 (PE14, PE15) Z* 4 OZ O O Z DRAK0, DRAK1 Z* 4 OO* 1 OO O* 1 DREQ0, DREQ1 Z* 4 IZ I I Z |
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