SH7041A datasheet(13/923 Pages) RENESAS

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Section

Page

Description

22.7.4 Erase-Verify

Mode

Figure 22.14

Erase/Erase-Verify

Flowchart

713

Figure amended

End of erasing

Start

Set SWE bit in FLMCR1

Set ESU1(2) bit in FLMCR1(2)

Set E1(2) bit in FLMCR1(2)

Wait 10

µs

Wait 200

µs

n = 1

Set EBR1(2)

Enable WDT

Wait 5 ms

Wait 10

µs

Wait 10

µs

Wait 20

µs

Set block start address to verify address

Wait 2

µs

Wait 5

µs

Start erase

Clear E1(2) bit in FLMCR1(2)

Clear ESU1(2) bit in FLMCR1(2)

Set EV1(2) bit in FLMCR1(2)

H'FF dummy write to verify address

Read verify data

Clear EV1(2) bit in FLMCR1(2)

Wait 5

µs

Clear EV1(2) bit in FLMCR1(2)

Clear SWE bit in FLMCR1

Disable WDT

Halt erase

Verify data = all "1"?

Last address of block?

End of

erasing of all erase

blocks?

Erase failure

Clear SWE bit in FLMCR1

≥ 60?

← n + 1

Increment

address

Notes: *1 Preprogramming (setting erase block data to all “0”) is not necessary.

*2 Verify data is read in 32-bit (longword) units.

*3 Set only one bit in EBR1(2). More than one bit cannot be set.

*4 Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.

*5 Make sure to set the wait times and repetitions as specified. Erasing may not complete correctly if values other

than the specified ones are used.

24.4.2 Canceling the

Standby Mode

747

Cancellation by a Manual Reset deleted

25. Electrical

Characteristics (5V,

33.3 MHz Version)

—

Deleted

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