SH7041A datasheet(76/923 Pages) RENESAS

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Table 1.7

Pin Functions (cont)

Classification

Symbol

I/O

Name

Function

Operating

mode control

MD0–MD3

Mode set

Determines the operating mode. Do

not change input value during

operation.

FWP

Flash memory

write protect

Protects flash memory from being

written or deleted.

Interrupts

NMI

Non-maskable

interrupt

Non-maskable interrupt request pin.

Enables selection of whether to

accept on the rising or falling edge.

IRQ0–

IRQ7

Interrupt

requests 0–7

Maskable interrupt request pins.

Allows selection of level input and

edge input.

IRQOUT

Interrupt request

output

Indicates that interrupt cause has

occurred. Enables notification of

interrupt generation also during bus

release.

Address bus

A0–A21

Address bus

Outputs addresses.

Data bus

D0–D15

(QFP-112)

D0–D31

(QFP-144)

I/O

Data bus

16-bit (QFP-112 pin and TQFP-120

pin versions) or 32-bit (QFP-144 pin

version) bidirectional data bus.

Bus control

CS0–CS3

Chip selects 0–3

Chip select signals for external

memory or devices.

Read

Indicates reading from an external

device.

WRH

Upper write

Indicates writing the upper 8 bits

(15–8) of external data.

WRL

Lower write

Indicates writing the lower 8 bits

(7–0) of external data.

WAIT

Wait

Input causes insertion of wait cycles

into the bus cycle during external

space access.

RAS

Row address

strobe

Timing signal for DRAM row

address strobe.

CASH

Upper column

address strobe

Timing signal for DRAM column

address strobe.

Output when the upper 8 bits of

data are accessed.

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