SH7041A datasheet(12/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section

Page

Description

22.7.2 Program-

Verify Mode

Figure 22.13

Program/Program

Verify Flow

706

Figure amended

Set SWE bit in FLMCR1

= 1

m = 0

Write 32-byte data in reprogram data area

in RAM to flash memory consecutively

Start of programming

Store 32-byte program data in

reprogram data area

Read verify data

Clear SWE bit in FLMCR1

m = 1

End of programming

Program data = verify data?

End of 32-byte

data verification?

flag = 0?

Verify

Increment address

Programming failure

Clear SWE bit in FLMCR1

≥ 1000

← n + 1

Start

End of programming

Enable WDT

Disable WDT

Reprogram data computation

Transfer reprogram data to reprogram

data area

Wait 10

µs

Clear PV1(2) bit in FLMCR1(2)

Wait 4

µs

Dummy write of H'FF to verify address

Wait 2

µs

Set PV1(2) bit in FLMCR1(2)

Wait 4

µs

Clear PSU1(2) bit in FLMCR1(2)

Wait 10

µs

Clear P1(2) bit in FLMCR1(2)

Wait 10

µs

Set P1(2) bit in FLMCR1(2)

Wait 200

µs

Set PSU1(2) bit in FLMCR1(2)

Wait 50

µs

Note *5 added.

*5 Make sure to set the wait times and repetitions as specified.

Programming may not complete correctly if values other than

the specified ones are used.

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