SH7041A datasheet(94/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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2.3.3

Instruction Format

Table 2.9 lists the instruction formats for the source operand and the destination operand. The

meaning of the operand depends on the instruction code. The symbols are used as follows:

• xxxx: Instruction code

• mmmm: Source register

• nnnn: Destination register

• iiii: Immediate data

• dddd: Displacement

Table 2.9

Instruction Formats

Source

Operand

Destination

Operand

Example

0 format

xxxx

——

NOP

n format

—

nnnn: Direct

MOVT

xxxx

nnnn

Control register

or system

nnnn: Direct

STS

MACH,Rn

Control register

or system

nnnn: Indirect pre-

decrement register

STC.L

SR,@-Rn

m format

mmmm: Direct

Control register or

system register

LDC

Rm,SR

xxxx

mmmm

xxxx

mmmm: Indirect

post-increment

Control register or

system register

LDC.L

@Rm+,SR

mmmm: Direct

—

JMP

@Rm

mmmm: PC

relative using Rm

—

BRAF

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