SH7041A datasheet(27/923 Pages) RENESAS

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9.4.4

Cache Hit after Cache Miss .................................................................................. 162

Section 10 Bus State Controller (BSC) ......................................................................... 163

10.1

Overview............................................................................................................................ 163

10.1.1 Features................................................................................................................. 163

10.1.2 Block Diagram...................................................................................................... 164

10.1.3 Pin Configuration ................................................................................................. 165

10.1.4 Register Configuration ......................................................................................... 166

10.1.5 Address Map......................................................................................................... 167

10.2

Description of Registers..................................................................................................... 169

10.2.1 Bus Control Register 1 (BCR1)............................................................................ 169

10.2.2 Bus Control Register 2 (BCR2)............................................................................ 172

10.2.3 Wait Control Register 1 (WCR1) ......................................................................... 175

10.2.4 Wait Control Register 2 (WCR2) ......................................................................... 177

10.2.5 DRAM Area Control Register (DCR) .................................................................. 178

10.2.6 Refresh Timer Control/Status Register (RTCSR) ................................................ 181

10.2.7 Refresh Timer Counter (RTCNT) ........................................................................ 183

10.2.8 Refresh Time Constant Register (RTCOR).......................................................... 184

10.3

Accessing Ordinary Space ................................................................................................. 185

10.3.1 Basic Timing......................................................................................................... 185

10.3.2 Wait State Control ................................................................................................ 186

10.3.3

CS Assert Period Extension.................................................................................. 188

10.4

DRAM Access ................................................................................................................... 189

10.4.1 DRAM Direct Connection.................................................................................... 189

10.4.2 Basic Timing......................................................................................................... 190

10.4.3 Wait State Control ................................................................................................ 191

10.4.4 Burst Operation..................................................................................................... 195

10.4.5 Refresh Timing ..................................................................................................... 197

10.5

Address/Data Multiplex I/O Space Access........................................................................ 199

10.5.1 Basic Timing......................................................................................................... 199

10.5.2 Wait State Control ................................................................................................ 200

10.5.3 CS Assertion Extension ........................................................................................ 201

10.6

Waits between Access Cycles ........................................................................................... 201

10.6.1 Prevention of Data Bus Conflicts ......................................................................... 201

10.6.2 Simplification of Bus Cycle Start Detection ........................................................ 203

10.7

Bus Arbitration................................................................................................................... 203

10.8

Memory Connection Examples ......................................................................................... 205

10.9

On-Chip Peripheral I/O Register Access........................................................................... 210

10.10 CPU Operation when Program is in External Memory ..................................................... 211

Section 11 Direct Memory Access Controller (DMAC) .......................................... 213

11.1

Overview............................................................................................................................ 213

11.1.1 Features................................................................................................................. 213

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