SH7041A datasheet(111/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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RES = 0

Power-on reset state

Manual reset state

Sleep mode

Standby mode

Program execution state

Bus release state

Exception processing state

RES = 1

MRES = 1

RES = 1

When an interrupt source

or DMA address error occurs

NMI interrupt

source occurs

Exception

processing

ends

Bus request

generated

Exception

processing

source occurs

Bus request

cleared

Bus request

generated

Bus request

cleared

SBY bit

cleared

for SLEEP

instruction

SBY bit set

for SLEEP

instruction

From any state

when

RES = 0

From any state when

RES = 1 and MRES = 0

Reset states

Power-down state

Bus request

generated

Bus request

cleared

Figure 2.6 Transitions between Processing States

Reset State: The CPU resets in the reset state. When the

RES pin level goes low, a power-on reset

results. When the

RES pin is high and MRES is low, a manual reset will occur.

Exception Processing State: The exception processing state is a transient state that occurs when

exception processing sources such as resets or interrupts alter the CPU’s processing state flow.

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