SH7041A datasheet(216/923 Pages) RENESAS

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• Bits 15–6—Reserved: These bits always read as 0. The write value should always be 0.

• Bits 5–4—DRAM Space DMA Single Address Mode Access Wait Specification (DDW1,

DDW0): Specifies the number of waits for DRAM space access during DMA single address

mode accesses. These bits are independent of the DWW and DWR bits of the DCR.

Bit 5 (DDW1)

Bit 4 (DDW0)

Description

2-cycle (no wait) external wait disabled

(initial value)

3-cycle (1 wait) external wait disabled

4-cycle (2 wait) external wait enabled

5-cycle (3 wait) external wait enabled

• Bits 3–0—CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2,

DSW1, DSW0): Specifies the number of waits for CS space access (0–15) during DMA single

address mode accesses. These bits are independent of the W bits of the WCR1.

Bit 3

(DSW3)

Bit 2

(DSW2)

Bit 1

(DSW1)

Bit 0

(DSW0)

Description

0000

No wait (external wait input disabled)

0001

1 wait (external wait input enabled)

⋅⋅⋅

1111

15 wait (external wait input enabled) (initial value)

10.2.5

DRAM Area Control Register (DCR)

DCR is a 16-bit read/write register that selects the number of waits, operation mode, number of

address multiplex shifts and the like for DRAM control.

Do not perform any DRAM space accesses before DCR initial settings are completed.

DCR is initialized by power-on resets to H'0000, but is not initialized by manual resets or software

standbys.

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