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SH7041A 数据表(PDF) 228 Page - Renesas Technology Corp |
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SH7041A 数据表(HTML) 228 Page - Renesas Technology Corp |
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228 / 923 page  190 10.4.2 Basic Timing The SH7040 Series supports 2 CAS format DRAM access. The DRAM access basic timing is a minimum of 3 cycles for normal mode. Figure 10.7 shows the basic DRAM access timing. DRAM space access is controlled by RAS, CASx, and RDWR signals. The following signals are associated with transfer of these actual byte locations: CASHH (bits 31–24), CASHL (bits 23–16), CASH (bits 15–8), and CASL (bits 7–0). However, the signals for ordinary space, WRx and RD, are also output during the DMAC single transfer column address cycle period. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc is the CAS assert cycle and Tc2 is the read data fetch cycle. Tp Tr Tc1 Tc2 CK Write Read Address Data RAS CASx RDWR Data RDWR CASx RAS Row Column Figure 10.7 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, No Waits) |
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