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SH7041A 数据表(PDF) 248 Page - Renesas Technology Corp |
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SH7041A 数据表(HTML) 248 Page - Renesas Technology Corp |
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248 / 923 page  210 SH704x 256k × 16 bits DRAM RAS RDWR A0 A1 A2–A10 CASHH CASHL AD16–AD31 RAS WE OE A0–A8 UCAS LCAS I/O0–I/O15 I/O0–I/O15 CASH CASL AD0–AD15 RAS WE OE A0–A8 UCAS LCAS Figure 10.31 32-Bit Data Bus Width DRAM Connection 10.9 On-Chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in table 10.6. Table 10.6 On-Chip Peripheral I/O Register Access On-chip Peripheral Module SCI MTU, POE INTC PFC, PORT CMT A/D* UBC WDT DMAC DTC CACHE Connected bus width 8bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit Access cycle 2cyc 2cyc 2cyc 2cyc 2cyc 2cyc 3cyc 3cyc 3cyc 3cyc 3cyc Note: * A/D of A mask products are accessed in 8-bit width, 3 cyc. |
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