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SH7041A 数据表(PDF) 280 Page - Renesas Technology Corp

部件名 SH7041A
功能描述  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SH7041A 数据表(HTML) 280 Page - Renesas Technology Corp

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242
Transfer
source
address (H)
Transfer
source
address (L)
Indirect
address
NOP
Transfer
destination
address
Indirect
address (H)
Indirect
address (L)
Transfer
data
Transfer
data
Transfer
data
Transfer
data
Transfer
data
Transfer source
address *1
Indirect address *2
Indirect
address
NOP
Indirect
address
Address read cycle
(1st)
(2nd)
(3rd)
NOP
cycle
Data
read cycle
(4th)
Data
write cycle
CK
A21–A0
CSn
D15–D0
Internal
address
bus
Internal
data bus
DMAC
indirect
address
buffer
DMAC
data
buffer
RD
WRH,
WRL
Notes:
*1
*2
The internal address bus is controlled by the port and does not change.
DMAC does not fetch value until 32-bit data is read from the internal data
bus.
External memory space has 16-bit width.
Figure 11.10 Dual Address Mode and Indirect Address Transfer Timing Example 1
(External Memory Space to External Memory Space)



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