SH7041A datasheet(285/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

285 / 923 page

247

DRAK is output once for the first

DREQ sampling, irrespective of transfer mode or DREQ

detection method. In burst mode, using edge detection,

DREQ is sampled for the first cycle only,

so DRAK is also output for the first cycle only. Therefore, the

DREQ signal negate timing can be

ascertained, and this facilitates handshake operations of transfer requests with the DMAC.

Cycle Steal Mode Operations: In cycle steal mode,

DREQ sampling timing is the same

irrespective of dual or single address mode, or whether edge or low-level

DREQ detection is used.

For example, DMAC transfer begins (figure 11.15), at the earliest, three cycles from the first

sampling timing. The second sampling begins at the start of the transfer one bus cycle prior to the

start of the DMAC transfer initiated by the first sampling (i.e., from the start of the CPU(3)

transfer). At this point, if DREQ detection has not occurred, sampling is executed every cycle

thereafter.

As in figure 11.16, whatever cycle the CPU transfer cycle is, the next sampling begins from the

start of the transfer one bus cycle before the DMAC transfer begins.

Figure 11.15 shows an example of output during DACK read and figure 11.16 an example of

output during DACK write.

SH7041A 数据表(PDF) 285 Page - Renesas Technology Corp