SH7041A datasheet(294/923 Pages) RENESAS

294 / 923 page

256

Burst Mode, Single Address, and Level Detection:

DREQ sampling timing in burst mode with

single address and level detection is shown in figures 11.21 and 11.22.

In burst mode with single address and level detection, a dummy cycle is inserted as one bus cycle,

at the earliest, three cycles after timing of the first sampling. Data during this period is undefined,

and the DACK signal is not output. Nor is the number of DMAC transfers counted. The actual

DMAC transfer begins after one dummy bus cycle output.

The dummy cycle is not counted either at the start of the second sampling (transfer one bus cycle

before the start of the first DMAC transfer). Therefore, the second sampling is not conducted from

the bus cycle starting the dummy cycle, but from the start of the CPU(3) bus cycle.

Thereafter, as long the

DREQ is continuously sampled, no dummy cycle is inserted. DREQ

sampling timing during this period begins from the start of the transfer one bus cycle before the

start of DMAC transfer, in the same way as with cycle steal mode.

As with the fourth sampling in figure 11.21, once DMAC transfer is interrupted, a dummy cycle is

again inserted at the start as soon as DMAC transfer is resumed.

The DACK output period in burst mode is the same as in cycle steal mode.

SH7041A 数据表(PDF) 294 Page - Renesas Technology Corp