MPC8343ECVRADDB datasheet(14/80 Pages) NXP

14 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

RESET Initialization

5.2

RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications of the MPC8343EA.

Table 11 lists the PLL and DLL lock times.

Table 10. RESET Initialization Timing Specifications

Parameter

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock applied to CLKIN when the

MPC8343EA is in PCI host mode

—

tCLKIN

Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN

when the MPC8343EA is in PCI agent mode

—

tPCI_SYNC_IN

HRESET/SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is

in PCI host mode

4—

tCLKIN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is

in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR configuration signals with respect to negation of HRESET

0—

—

Time for the MPC8343EA to turn off POR configuration signals with respect to the

assertion of HRESET

—4

Time for the MPC8343EA to turn on POR configuration signals with respect to the

negation of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied

to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 11. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs—

DLL lock times

7680

122,880

csb_clk cycles

1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio

results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”

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