MPC8343ECVRADDB datasheet(49/80 Pages) NXP

49 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

Package and Pin Listings

Figure 34 and Figure 35 represent the AC timings from Table 50. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 34 shows the SPI timings in slave mode (external clock).

Figure 34. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 35 shows the SPI timings in master mode (internal clock).

Figure 35. SPI AC Timing in Master Mode (Internal Clock) Diagram

18 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8343EA is available

in a plastic ball grid array (PBGA). See Section 18.1, “Package Parameters for the MPC8343EA PBGA,”

and Section 18.2, “Mechanical Dimensions for the MPC8343EA PBGA.”

18.1

Package Parameters for the MPC8343EA PBGA

The package parameters are as provided in the following list. The package type is 29 mm

× 29 mm,

620 plastic ball grid array (PBGA).

Package outline

29 mm

× 29 mm

Interconnects

620

Pitch

1.00 mm

Module height (maximum)

2.46 mm

SPICLK (Input)

tNEIXKH

tNEIVKH

tNEKHOX

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

SPICLK (Output)

tNIIXKH

tNIKHOX

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

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