MPC8343ECVRADDB datasheet(79/80 Pages) NXP

79 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

Document Revision History

11/2006

• Updated note in introduction.

• In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA

parts for all silicon revisions.

• In Table 57, “Suggested PLL Configurations,” added the following row:

• Ref No: 823, SPMF: 1000, Core PLL: 0100011, 400-MHz Device Input Clock Freq: 33, CSB

Freq: 266, and Core Freq: 400.

• In Section 23, “Ordering Information,” replicated note from document introduction.

8/2006

• Changed all references to revision 2.0 silicon to revision 3.0 silicon.

• Changed number of general purpose parallel I/O pins to 39 in Section 1, “Overview.”

• Changed VIH minimum value in Table 35, “JTAG Interface DC Electrical Characteristics,” to

OVDD –0.3.

• In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min =

2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min

= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min

= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”

•

4/2006

• Removed Table 20, “Timing Parameters for DDR2-400.”

• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC

Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.

• Changed Min and Max values for VIH and VIL in Table 40Table 44,“PCI DC Electrical

Characteristics.”

• In Table 58, “MPC8343EA (PBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout

Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that

MDICO be tied to GRD using an 18

Ω resistor and MCIC1 be tied to DDR power using an 18 Ω

resistor.’

• Table 58, “MPC8343EA (PBGA) Pinout Listing,” in row AVDD3 changed power supply from

“AVDD3” to ‘—.’

3/2006

Initial public release

Table 64. Document Revision History (continued)

Rev.

Number

Date

Substantive Change(s)

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