MPC8343ECVRADDB datasheet(15/80 Pages) NXP

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8343EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.

The AC electrical specifications are the same for DDR and DRR2 SDRAM.

NOTE

The information in this document is accurate for revision 3.0 silicon and

later. For information on revision 1.1 silicon and earlier versions see the

MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware

Specifications. See Section 22.1, “Part Numbers Fully Addressed by This

Document,” for silicon revision level determination.

6.1

DDR and DDR2 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

MPC8343EA when GVDD(typ) = 1.8 V.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

1.71

1.89

I/O reference voltage

MVREF

0.49

× GV

0.51

× GV

I/O termination voltage

VTT

MVREF –0.04

MVREF +0.04

Input high voltage

VIH

MVREF + 0.125

GVDD +0.3

—

Input low voltage

VIL

–0.3

MVREF –0.125

—

Output leakage current

IOZ

–9.9

9.9

μA4

Output high current (VOUT = 1.420 V)

IOH

–13.4

—

Output low current (VOUT = 0.280 V)

IOL

13.4

—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise

on MVREF cannot exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal

MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ V

OUT ≤ GVDD.

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