MPC8343ECVRADDB datasheet(73/80 Pages) NXP

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

System Design Information

RθJC = junction-to-case thermal resistance (°C/W)

PD = power dissipation (W)

21 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8343EA.

21.1

System Clocking

The MPC8343EA includes two PLLs:

1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The

frequency ratio between the platform and CLKIN is selected using the platform PLL ratio

configuration bits as described in Section 19.1, “System PLL Configuration.”

2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e300 core clock and the platform clock is selected using the e300 PLL ratio

configuration bits as described in Section 19.2, “Core PLL Configuration.”

21.2

PLL Power Supply Filtering

Each PLL gets power through independent power supply pins (AVDD1, AVDD2, respectively). The AVDD

level should always equal to VDD, and preferably these voltages are derived directly from VDD through a

low frequency filter scheme.

There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to

provide four independent filter circuits as illustrated in Figure 38, one to each of the four AVDD pins.

Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.

The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built

with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the

recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic

(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value

capacitor.

To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the

specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD

pin, which is on the periphery of package, without the inductance of vias.

Figure 38 shows the PLL power supply filter circuit.

Figure 38. PLL Power Supply Filter Circuit

VDD

AVDD (or L2AVDD)

2.2 µF

GND

Low ESL Surface Mount Capacitors

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