MPC8343ECVRADDB datasheet(75/80 Pages) NXP

75 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

System Design Information

OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in value. Then, Z0 = (RP + RN) ÷ 2.

Figure 39. Driver Impedance Measurement

Two measurements give the value of this resistance and the strength of the driver current source. First, the

output voltage is measured while driving logic 1 without an external differential termination resistor. The

measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1

with an external precision differential termination resistor of value Rterm. The measured voltage is

V2 =(1 ÷ (1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1 ÷ V2 –1).

The drive current is then Isource =V1 ÷ Rsource.

Table 61 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,

nominal OVDD, 105°C.

21.6

Configuration Pin Multiplexing

The MPC8343EA power-on configuration options can be set through external pull-up or pull-down

resistors of 4.7 k

Ω on certain output pins (see the customer-visible configuration pins). These pins are used

as output only pins in normal operation.

Table 61. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI Signals

(Not Including PCI

Output Clocks)

PCI Output Clocks

(Including

PCI_SYNC_OUT)

DDR DRAM

Symbol

Unit

42 Target

25 Target

42 Target

20 Target

42 Target

25 Target

42 Target

20 Target

Differential

ZDIFF

Note: Nominal supply voltages. See Table 1, Tj = 105°C.

OVDD

OGND

Pad

Data

SW1

SW2

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