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MPC8343ECVRADDB 数据表(PDF) 64 Page - NXP Semiconductors

部件名 MPC8343ECVRADDB
功能描述  MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications
PDF  80 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MPC8343ECVRADDB 数据表(HTML) 64 Page - NXP Semiconductors

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
64
Freescale Semiconductor
Clocking
High
0010
2 : 1
133
High
0011
3 : 1
100
200
High
0100
4 : 1
133
266
High
0101
5 : 1
166
333
High
0110
6 : 1
200
High
0111
7 : 1
233
High
1000
8 : 1
1 CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT.
2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.
Table 56. CSB Frequency Options for Agent Mode
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk :
Input Clock Ratio2
Input Clock Frequency (MHz)2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2 : 1
133
Low
0011
3 : 1
100
200
Low
0100
4 : 1
100
133
266
Low
0101
5 : 1
125
166
333
Low
0110
6 : 1
100
150
200
Low
0111
7 : 1
116
175
233
Low
1000
8 : 1
133
200
266
Low
1001
9 : 1
150
225
300
Low
1010
10 : 1
166
250
333
Low
1011
11 : 1
183
275
Low
1100
12 : 1
200
300
Low
1101
13 : 1
216
325
Low
1110
14 : 1
233
Low
1111
15 : 1
250
Low
0000
16 : 1
266
High
0010
4 : 1
100
133
266
Table 55. CSB Frequency Options for Host Mode (continued)
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk :
Input Clock Ratio2
Input Clock Frequency (MHz)2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)



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