MPC8343ECVRADDB datasheet(59/80 Pages) NXP

59 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

Package and Pin Listings

OVDD

B27, D3, D11, D19, E15, E23, F5, F8,

F11, F14, F17, F20, G24, H23, H24, J6,

J14, J17, J18, K4, L9, L20, L23, L25, M6,

M9, M20, P5, P20, P23, R6, R9, R24,

U23, V4, V6

PCI, 10/100

Ethernet, and

other standard

(3.3 V)

OVDD

—

MVREF1

AF19

DDR

reference

voltage

—

MVREF2

AE10

DDR

reference

voltage

—

No Connection

A22, A23, A24, B22, B23, B24, C21,

C22, C23, C24, D21, D22, D23, D24,

E21, M27, M28, N26, N27, N28, P25,

P26, P27, R28, T24, T25, T26, T27, T28,

U27, U28, Y3, Y4, Y5, AA1, AA2, AA3,

AA4, AB1, AB2, AB3, AB4, AC1, AC2,

AC3, AC4, AD1, AD2, AD3, AD5, AD7,

AD11, AD12, AE4, AE6, AE8, AE9,

AE23, AF1, AF5, AF6, AF8, AF24, AG1,

AG3, AG4, AG7, AG8, AG9, AG10, AH2,

AH3, AH5, AH8, AH9, V5, V2, V1

——

—

Notes:

1. This pin is an open-drain signal. A weak pull-up resistor (1 k

Ω) should be placed on this pin to OV

DD.

2. This pin is an open-drain signal. A weak pull-up resistor (2–10 k

Ω) should be placed on this pin to OV

DD.

3. During reset, this output is actively driven rather than three-stated.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.

6. This pin must be always be tied to GND.

7. This pin must always be pulled up to OVDD.

8. Thermal sensitive resistor.

9. It is recommended that MDIC0 be tied to GND using an 18.2

Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω

resistor.

10.TSEC1_TXD[3] is required an external pull-up resistor. For proper functionality of the device, this pin must be pulled up or

actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net.

11. A weak pull-up resistor (2–10 k

Ω) should be placed on this pin to LV

DD1.

12. For systems that boot from local bus (GPCM)-controlled NOR flash, a pull up on LGPL4 is required.

Table 51. MPC8343EA (PBGA) Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

MPC8343ECVRADDB 数据表(PDF) 59 Page - NXP Semiconductors

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