MPC8343ECVRADDB datasheet(18/80 Pages) NXP

18 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

DDR and DDR2 SDRAM

Figure 5 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.

Figure 5. DDR Input Timing Diagram

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 20 shows the DDR and DDR2 output AC timing specifications.

266 MHz

–750

750

—

200 MHz

–750

750

—

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the equation: tDISKEW = ± (T/4 – abs (tCISKEW)); where T is the clock period and abs (tCISKEW) is the absolute

value of tCISKEW.

3. This specification applies only to the DDR interface.

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time, (MCK[n]/MCK[n] crossing)

tMCK

7.5

ADDR/CMD/MODT output setup with respect to MCK

tDDKHAS

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications (continued)

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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