MPC8343ECVRADDB datasheet(44/80 Pages) NXP

44 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

PCI

Table 42 provides the PCI AC timing specifications at 33 MHz.

Figure 30 provides the AC test load for PCI.

Figure 30. PCI AC Test Load

Input hold from clock

tPCIXKH

—

3, 5

Notes:

1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a

description of M66EN.

2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with

respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going

to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went

high (H) relative to the frame signal (F) going to the valid (V) state.

3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the

component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

Table 42. PCI AC Timing Specifications at 33 MHz

Parameter

Symbol1

Min

Max

Unit

Notes

Clock to output valid

tPCKHOV

—11

Output hold from clock

tPCKHOX

2—

Clock to output high impedance

tPCKHOZ

—14

2, 3

Input setup to clock

tPCIVKH

3.0

—

2, 4

Input hold from clock

tPCIXKH

—

2, 4

Notes:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with

respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going

to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went

high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the

component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

Table 41. PCI AC Timing Specifications at 66 MHz1 (continued)

Parameter

Symbol2

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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