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MPC8343ECVRADDB 数据表(PDF) 11 Page - NXP Semiconductors |
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MPC8343ECVRADDB 数据表(HTML) 11 Page - NXP Semiconductors |
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11 / 80 page  MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 11 Clock Input Timing Table 5 shows the estimated typical I/O power dissipation for MPC8343EA. 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the device. 4.1 DC Electrical Characteristics Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8343EA. Table 5. MPC8343EA Typical I/O Power Dissipation Interface Parameter DDR2 GVDD (1.8 V) DDR1 GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Unit Comments DDR I/O 65% utilization 2.5 V Rs = 20 Ω Rt = 50 Ω 2 pair of clocks 200 MHz, 32 bits 0.31 0.42 — — — W — 266 MHz, 32 bits 0.35 0.5 — — — W — PCI I/O load = 30 pF 33 MHz, 32 bits — — 0.04 — — W — 66 MHz, 32 bits — — 0.07 — — W — Local bus I/O load = 25 pF 167 MHz, 32 bits — — 0.34 — — W — 133 MHz, 32 bits — — 0.27 — — W — 83 MHz, 32 bits — — 0.17 — — W — 66 MHz, 32 bits — — 0.14 — — W — 50 MHz, 32 bits — — 0.11 — — W — TSEC I/O load = 25 pF MII — — 0.01 — W Multiply by number of interfaces used. GMII or TBI — — 0.06 — W RGMII or RTBI — — — 0.04 W USB 12 MHz — — 0.01 — — W — 480 MHz — — 0.2 — — W — Other I/O — — 0.01 — — W — Table 6. CLKIN DC Timing Specifications Parameter Condition Symbol Min Max Unit Input high voltage — VIH 2.7 OVDD +0.3 V Input low voltage — VIL –0.3 0.4 V CLKIN input current 0 V ≤ V IN ≤ OVDD IIN — ±10 μA |
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