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ADP5003ACPZ-R7 数据表(PDF) 29 Page - Analog Devices

部件名 ADP5003ACPZ-R7
功能描述  Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO
PDF  31 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5003ACPZ-R7 数据表(HTML) 29 Page - Analog Devices

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Data Sheet
ADP5003
Rev. A | Page 29 of 31
ADAPTIVE HEADROOM
The ADP5003 features a scheme to control the buck regulator
output voltage and thus the LDO headroom voltage to provide
better efficiency with the same noise performance of a standalone
LDO regulator. When the buck regulator uses the adaptive
headroom control configuration, the ADP5003 manages the
buck regulator output voltage vs. the LDO load current (see
Figure 25). The adaptive headroom control also optimizes the
LDO headroom when the remote sense feedback corrects any
output voltage drop due to additional filtering or high trace
impedance under high load conditions. The headroom profile
of the adaptive headroom control is set to deliver a consistent
PSRR across the load range while optimizing efficiency of the
overall system (see Figure 51). To enable adaptive headroom
control, connect VSET1 to VREG (see Figure 52).
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
LDO PSRR
VPVIN1 = 12V, VPVOUT2 = 0.9V
0.2V, 1A
0.28V, 1.5A
0.35V, 2A
0.4V, 2.5A
0.4V, 3A
Figure 51. LDO PSRR vs. Frequency
L1
2.2µH
CC
2.2nF
RC
1.74kΩ
RBOT2
64.9kΩ
ANALOG DEVICES
RF TRANSCEIVER,
HIGH SPEED ADC/DAC,
CLOCK, ASIC/
PROCESSOR
RT
VOUT1
SW1
SW1
SW1
PGND1
PGND1
PGND1
VREG
PVINSYS
VPVINSYS: 12V
AGND1
AGND2
PVIN2
PVIN2
PVIN2
PVOUT2
PVOUT2
PVOUT2
VFB2P
EN1
VBUF
COMP1
REFOUT
EN2
VFB2N
VSET2
LOW NOISE
LDO ACTIVE
FILTER
3A
SYNC
VSET1
PVIN1
PVIN1
BUCK
REGULATOR
3A
VPVIN1: 12V
CVREG
1µF
CVBUF
0.1µF
CVREG_LDO
1µF
SYSTEM
PWRGD
VREG_LDO
VVPOUT2 = 1.3V
VPVOUT1
(ADAPTIVE)
RRT
294kΩ
RTOP2
100kΩ
CPVIN1
10µF
CPVINSYS
10µF
CPVOUT1
47µF
CPVIN2
10µF
CPVOUT2
10µF
CREFOUT
0.22µF
Figure 52. Adaptive Headroom Configuration



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