ADP5003ACPZ-R7 datasheet(19/31 Pages) AD

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Data Sheet

ADP5003

Rev. A | Page 19 of 31

The minimum off time limits the maximum duty cycle which

in turn limits the maximum output voltage for a given input

voltage and switching frequency. Calculate the maximum output

voltage for a given input voltage and switching frequency by

using the following equation:

VOUT_MAX = VPVIN1 × (1 − tMIN_OFF × fSW) − (RPFET – RNFET) × IOUT_MAX ×

(1 − tMIN_OFF × fSW) − (RNFET + RL) × IOUT_MAX

(5)

where:

VOUT_MAX is the maximum output voltage.

IOUT_MAX is the maximum output current.

tMIN_OFF is the minimum off time.

As shown in Equation 4 and Equation 5, reducing the switching

frequency eases the minimum on time and minimum off time

limitations.

COMPONENT SELECTION

Output Capacitors

Higher output capacitor values reduce the output voltage ripple

and improve the load transient response.

Ceramic capacitors are manufactured with a variety of dielectrics,

each with a different behavior over temperature and applied

voltage. Capacitors must have a dielectric adequate to ensure

the minimum capacitance over the necessary temperature range

and dc bias conditions. X5R or X7R dielectrics with a voltage

rating of 25 V are recommended for best performance. Y5V

and Z5U dielectrics are not recommended for use with any dc-

to-dc converter because of their poor temperature and dc bias

characteristics.

Use the following equation to calculate the worst case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage:

CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×

(1 − Tolerance)

(6)

where:

CEFFECTIVE is the effective capacitance at the operating voltage.

CNOMINAL is the nominal data sheet capacitance.

TEMPCO is the worst case capacitor temperature coefficient.

DCBIASCO is the dc bias derating at the output voltage.

Tolerance is the worst case component tolerance.

To guarantee the performance of the device, it is imperative to

evaluate the dc bias effects, temperature, and tolerances on the

behavior of the capacitors for each application.

Capacitors with lower effective series resistance (ESR) and

effective series inductance (ESL) are preferred to minimize

output voltage ripple.

Use the following equation to calculate the minimum

capacitance needed for a specific output voltage ripple:

)

(

—

ESR

RIPPLE

OUT_MIN

ΔI

≅

(7)

where:

ΔIL is the current ripple.

fSW is the switching frequency.

VRIPPLE is the allowed peak-to-peak voltage ripple.

RESR is the effective series resistance of the capacitor.

The minimum capacitance needed for stability considering

temperature and dc bias effects is 22 µF.

The minimum capacitance recommended for the LDO is 10 µF.

Table 8. Recommended Output Capacitors

Vendor

Part No.

Value (µF)

Type

Voltage Rating (V)

Case

Wurth

885 012 207 026

X7R

0805

885 012 209 006

X7R

1210

885 012 109 012

X5R

1210

885 012 109 004

100

X5R

6.3

1210

Murata

GRM21BR71A106KE51

X7R

0805

GRM32ER71C226KEA8

X7R

1210

GRM32ER71A476KE15

X7R

1210

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