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ADP5003ACPZ-R7 数据表(PDF) 7 Page - Analog Devices

部件名 ADP5003ACPZ-R7
功能描述  Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO
PDF  31 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5003ACPZ-R7 数据表(HTML) 7 Page - Analog Devices

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Data Sheet
ADP5003
Rev. A | Page 7 of 31
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Rating
PVIN1/PVINSYS to AGND1/AGND2
−0.3 V to +16 V
PVIN2 to AGND1/AGND2
−0.3 V to +6.0 V
AGND1 to AGND2
−0.3 V to +0.3 V
PGND1 to AGND1/AGND2
−0.3 V to +0.3 V
PVOUT2 to AGND1/AGND2
−0.3 V to the lower of
(PVIN2 + 0.3 V) or +6.0 V
VFB2N to AGND1/AGND2/PGND1
−0.3 V to +0.3 V
VOUT1, VFB2P, EN1, EN2, SYNC, RT,
REFOUT, VBUF, VSET1, VSET2,
COMP1 to AGND1/AGND2
−0.3 V to the lower of (VREG
+ 0.3 V) or +6.0 V
SW1 to PGND1
−0.3 V to (PVIN1 + 0.3 V)
VREG, VREG_LDO to
AGND1/AGND2/PGND1/VFB2N
−0.3 V to the lower of
(PVINSYS + 0.3 V) or +6.0 V
VREG to VREG_LDO
−0.3 V to +0.3 V
Storage Temperature Range
−65°C to +150°C
Operating Junction Temperature
Range
−40°C to +125°C
Soldering Conditions
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Table 6. Thermal Resistance
Package Type
θJA1
θJC1
Unit
CP-32-7
46.91
20.95
°C/W
1
θJA and θJC are based on a 4-layer PCB (two signal and two power planes)
with nine thermal vias connecting the exposed pad to the ground plane as
recommended in the Layout Considerations section.
ESD CAUTION



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