ADP5003ACPZ-R7 datasheet(21/31 Pages) AD

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Data Sheet

ADP5003

Rev. A | Page 21 of 31

COMPENSATION COMPONENTS DESIGN

For the peak current mode control architecture, the power stage

can be simplified as a voltage controlled current source that

supplies current to the output capacitor and load resistor. The

simplified loop is composed of one dominant pole and a zero

contributed by the output capacitor ESR.

The ADP5003 uses a transconductance amplifier as the error

amplifier to compensate the system. Figure 46 shows the

simplified peak current mode control, small signal circuit.

RESR

–

CCP

CPVOUT1

RTOP1

RBOT1

–

AVI

VPVOUT1

VCOMP1

ABUCK

VSET1

VREFOUT

VPVOUT1

Figure 46. Simplified Peak Current Mode Control, Small Signal Circuit

The compensation components, RC and CC, contribute a zero,

and the optional CCP and RC contribute an optional pole.

The following procedure shows how to select the compensation

components (RC, CC, and CCP) for ceramic output capacitor

applications:

1. Determine the cross frequency (fC). Generally, fC is

between fSW/12 and fSW/6.

2. Use the following equation to calculate RC:

BUCK

PVOUT

(10)

where:

CPVOUT1 is the output capacitance.

AVI = 7 A/V.

3. Place the compensation zero at the domain pole (fP).

Determine CC as follows:

CC = ((R + RESR) × CPVOUT1)/RC

(11)

where:

RESR is the equivalent series resistance of the output

capacitor.

4. CCP is optional. It can cancel the zero caused by the ESR of

the output capacitor. Determine CCP as follows:

CCP = (RESR × CPVOUT1)/RC

(12)

JUNCTION TEMPERATURE

In cases where the ambient temperature (TA) is known, the

thermal resistance parameter (θJA) can estimate the junction

temperature rise (TJ). TJ is calculated with TA and the power

dissipation (PD) using the following formula:

TJ = TA + (PD × θJA)

(13)

The typical θJA value for the 32-lead, 5 mm × 5 mm LFCSP is

46.91°C/W. An important factor to consider is that θJA is based

on a 4-layer, 4 inches × 3 inches, 2.5 ounces copper PCB, as per

the JEDEC standard, and applications may use different sizes

and layers. It is important to maximize the copper used to

remove the heat from the device. Copper exposed to air

dissipates heat better than copper used in the inner layers.

Connect the exposed pad to the ground plane with several vias.

If the case temperature can be measured, the junction

temperature is calculated by

TJ = TC + (PD × θJC)

(14)

where:

TC is the case temperature.

θJC is the junction to case thermal resistance provided in Table 6.

To achieve reliable operation of the buck converter and LDO

regulator, the estimated die junction temperature of the

ADP5003 must be less than 125°C. Reliability and mean time

between failures (MTBF) is highly affected by increasing the

junction temperature. Additional information about product

reliability can be found in the Analog Devices, Inc., Reliability

Handbook at www.analog.com/reliability_handbook.

The total power dissipation in the ADP5003 simplifies to

PD = PDBUCK + PDLDO

(15)

where:

PDBUCK = (VPVIN1 × IPVIN1) − (VPVOUT1 × ILOAD1).

PDLDO = ((VPVIN2 − VPVOUT2) × ILOAD2) + (VPVIN2 × IGND).

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