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Data Sheet

ADP5003

Rev. A | Page 15 of 31

THEORY OF OPERATION

POWER MANAGEMENT UNIT

The ADP5003 is a micropower management unit combining a

step-down (buck) dc-to-dc converter and an ultralow noise low

dropout linear (LDO)regulator. The high switching frequency

and 5 mm × 5 mm, 32-lead LFCSP package allow a compact

power management solution.

Adaptive Headroom Control

The ADP5003 features a scheme to control the LDO headroom

voltage to ensure optimal operating efficiency while maintaining a

consistent power supply rejection ratio (PSRR) across the full

range of the LDO load current.

The scheme works by varying the headroom voltage across the

LDO NFET with respect to the LDO load current. Lower and

upper limits prevent the headroom from approaching zero volts

at light loads and from increasing more than necessary at high

loads.

Precision Enable/Shutdown

The ADP5003 has individual enable pins (EN1 and EN2) to

control the regulators.

The precision enable function allows a precise turn on point for

the regulators to allow the possibility of external sequencing. A

voltage level higher than VTH_H applied to the EN1 or EN2 pin

activates a regulator, whereas a level below VTH_L turns off a

regulator. The buck is controlled by EN1, and the LDO is

controlled by the EN2 pin. When both EN1 and EN2 fall below

VTH_S, the ADP5003 enters shutdown mode.

Undervoltage Lockout (UVLO)

To protect against the input voltage being too low, UVLO

circuitry is integrated into the system. If the input voltage on

PVINSYS drops to less than the UVLOPVINSYSFALL threshold, all

channels shut down.

The device is enabled again when the voltage on PVINSYS rises

to more than the UVLOPVINSYSRISE threshold, provided the enable

pins remain active.

Thermal Shutdown (TSD)

In the event that the junction temperature rises above TSD, the

thermal shutdown circuit turns off both regulators. Extreme

junction temperatures can be the result of high current operation,

poor circuit board design, or a high ambient temperature. A

hysteresis value of TSD-HYS is included so that when thermal

shutdown occurs, the regulators do not return to operation until

the on-chip temperature drops below TSD − TSD-HYS. When

emerging from thermal shutdown, both regulators restart with

soft start control.

Active Pull Down

Both regulators have active pull-down resistors discharging the

respective output capacitors when the regulators are disabled.

The pull-down resistors are connected between VOUT1 to

AGND1 and PVOUT2 to AGND2. Active pull-down resistors

are disabled when the regulators are turned on.

When the enable pins are asserted low, or a TSD or UVLO

event occurs, the active pull-down resistors enable to quickly

discharge the output capacitors. The pull-down resistors remain

engaged until the enable pins are asserted high, the fault event is

no longer present, or the VREG supply voltage falls to less than

the voltage required (approximately 1 V) to guarantee that the

pull-down resistor remains enabled.

Soft Start (SS)

Both regulators have an internal soft start function that ramps

the output voltage in a controlled manner on startup, thereby

limiting the inrush current. The soft start function reduces the

risk of noise spikes and voltage drops on the upstream supplies.

Power-Good

The ADP5003 has a dedicated power-good, open-drain, output

(PWRGD). PWRGD indicates whether one or more regulators

are outside the voltage limits specified by the power-good lower

limit (PWRGDF) and the power-good upper limit (PWRGDF +

PWRGDFH). When either one or both of the regulator outputs

are outside the power-good limits, the PWRGD output pulls low.

PWRGD will continue to pull low, provided the VREG supply

voltage remains above approximately 1 V.

When in adaptive mode, PWRGD only monitors the LDO

output, and when in standalone mode, PWRGD only monitors

the regulator/regulators that are enabled.

BUCK REGULATOR

Control Scheme

The buck regulator operates with a fixed frequency, emulated

peak current mode, pulse-width modulation (PWM) control

architecture, where the duty cycle of the integrated switches is

adjusted and regulates the output voltage. At the start of each

oscillator cycle, the positive channel field effect transistor (PFET)

switch is turned on, sending a positive voltage across the inductor.

Current in the inductor increases until the emulated current

sense signal crosses the peak inductor current threshold, which

turns off the PFET switch and turns on the NFET synchronous

rectifier. Turning on the NFET synchronous rectifier creates a

negative voltage across the inductor, which causes the inductor

current to decrease. The synchronous rectifier stays on for the

remainder of the cycle. By adjusting the peak inductor current

threshold, the buck regulator can regulate the output voltage.

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