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ADP5003ACPZ-R7 数据表(PDF) 30 Page - Analog Devices |
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ADP5003ACPZ-R7 数据表(HTML) 30 Page - Analog Devices |
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30 / 31 page  ADP5003 Data Sheet Rev. A | Page 30 of 31 LAYOUT CONSIDERATIONS Layout is important for all switching regulators but is particularly important for regulators with high switching frequencies. To achieve high efficiency, proper regulation, stability, and low noise, a well designed PCB layout is required. Follow these guidelines when designing PCBs: • Keep high current loops as short and wide as possible. • Keep the input bypass capacitors close to the PVIN1, PVIN2, and PVINSYS pins. • Keep the inductor and output capacitor close to SW1 and PGND1. • Route the VFB2P and VFB2N LDO sense traces side by side connecting them each as close as possible to the point of load. Keep them as short as possible and away from noise sources. • Place the frequency setting resistor close to the RT pin. Keep AGND1 and PGND1 separate on the top layer of the board. This separation avoids pollution of AGND1 with switching noise. Do not connect PGND1 to the EPAD on the top layer of the layout. Connect both AGND1 and PGND1 to the board ground plane with vias. Ideally, connect PGND1 to the plane at a point between the input and output capacitors. • Connect the negative terminal of CVBUF to the VFB2N pin. ADP5003 CVOUT1 22µF 25V/X5R 1206 CPVIN2 10µF 50V/X5R 1206 0201 0201 0201 0402 0402 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 PVIN PVOUT2 13.2mm L1 CPVINSYS 10µF 35V/X5R 0805 CPVIN1 10µF 50V/X5R 1206 CVREG 1µF 10V/X5R 0406 CC CCP RRT RC RBOT2 RTOP2 RBOT1 RTOP1 CREFOUT 0.22µF 10V/X5R 0402 CVBUF 0.1µF 10V/X5R 0402 CVREG_LDO 1µF 10V/X5R 0402 CPVOUT2 10µF 25V/X5R 0805 Figure 53. Example Outline Layout |
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