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ADP5003ACPZ-R7 数据表(PDF) 18 Page - Analog Devices

部件名 ADP5003ACPZ-R7
功能描述  Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO
PDF  31 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5003ACPZ-R7 数据表(HTML) 18 Page - Analog Devices

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ADP5003
Data Sheet
Rev. A | Page 18 of 31
POWER-GOOD
An external pull-up resistor is necessary to drive the PWRGD
output high (see Figure 43). Through the value of the pull-up
resistor is not critical, it is recommended to use a 10 kΩ to
300 kΩ resistor. The resistor must be pulled to a voltage level
no greater than 5.5 V.
PWRGD
GPIO
RPULLUP
VPWRGD
VPULLUP
Figure 43. Power-Good Setup
OUTPUT VOLTAGE OF THE BUCK REGULATOR
The output voltage on the buck regulator is adjustable through
an external resistor divider. When using adaptive mode, the
ADP5003 controls the buck output voltage.
The adjustable output voltage configuration is shown in Figure 44.
BUCK
RTOP1
RBOT1
VSET1
SW1
PVIN1
REFOUT
VOUT1
PVOUT1
Figure 44. Buck Regulator Adjustable Output Voltage
To calculate the buck output voltage, use the following equation:
1
1
1
1
BOT
TOP
BOT
BUCK
REFOUT
PVOUT
R
R
R
A
V
V
(2)
where:
VREFOUT is the REFOUT output voltage.
ABUCK is the buck regulator gain.
RBOT1 is the bottom divider resistor.
RTOP1 is the top divider resistor.
OUTPUT VOLTAGE OF THE LDO REGULATOR
The output voltage on the LDO regulator is adjustable through
an external resistor divider. The LDO adjustable output voltage
configuration is shown in Figure 45.
LDO
RTOP2
RBOT2
VSET2
PVIN2
REFOUT
VFB2P
VFB2N
PVOUT2
Figure 45. LDO Adjustable Output Voltage Configuration
To calculate the LDO output voltage, use the following
equation:
2
2
2
2
BOT
TOP
BOT
LDO
REFOUT
PVOUT
R
R
R
A
V
V
(3)
where:
ALDO is the LDO gain.
RBOT2 is the bottom divider resistor.
RTOP2 is the top divider resistor.
VOLTAGE CONVERSION LIMITATIONS
For a given input voltage and switching frequency, an upper
and lower limitation on the output voltage exists due to the
minimum on time and minimum off time. The minimum on
time limits the minimum output voltage for a given input
voltage and switching frequency.
If the minimum on time is exceeded, the ADP5003 may not
switch at a fixed frequency because the device can switch at an
effective zero on time, resulting in unpredictable switching
frequencies and unwanted noise.
To calculate the minimum output voltage for a given input
voltage and fixed switching frequency, use the following
equation:
VOUT_MIN = VPVIN1 × tMIN_ON × fSW − (RPFET – RNFET) ×
IOUT_MIN × tMIN_ON × fSW − (RNFET + RL) × IOUT_MIN
(4)
where:
VOUT_MIN is the minimum output voltage.
VPVIN1 is the input voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RPFET is the high-side PFET on resistance.
RNFET is the low-side NFET on resistance.
IOUT_MIN is the minimum output current.
RL is the resistance of the output inductor.



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