ADP5003

Data Sheet

Rev. A | Page 8 of 31

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. EXPOSED THERMAL PAD. CONNECT THE

EXPOSED THERMAL PAD TO AGND1.

24 AGND1

23 VREG

22 RT

21 COMP1

20 PWRGD

19 VSET1

18 REFOUT

17 VSET2

1

2

3

4

5

6

7

8

PGND1

VOUT1

EN1

EN2

SYNC

PVIN2

PVIN2

PVIN2

ADP5003

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 31, 32

PGND1

Buck Regulator Dedicated Power Ground.

2

VOUT1

Buck Regulator Feedback Input. Connect a short sense trace to the buck output capacitor.

3

EN1

Buck Regulator Precision Enable Pin. Drive the EN1 pin high to turn on the buck regulator, and drive the EN1 pin

low to turn off the buck regulator.

4

EN2

LDO Precision Enable Pin. Drive the EN2 pin high to turn on the LDO regulator, and drive the EN2 pin low to turn

off the LDO regulator.

5

SYNC

Synchronization Input. To synchronize the switching frequency of the device to an external clock, connect this

pin to an external clock with a frequency from 300 kHz to 2.5 MHz.

6 to 8

PVIN2

LDO Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and AGND2.

9 to 11

PVOUT2

LDO Regulator Power Output. Connect a 10 µF ceramic capacitor between this pin and AGND2.

12

VFB2P

LDO Regulator Positive Sense Feedback Input. Connect a sense trace to the LDO output at the load. Route this

pin alongside the VFB2N pin on the PCB.

13

VFB2N

LDO Regulator Ground Sense Feedback Input. Connect a sense trace to ground at the load. Route this pin

alongside the VFB2P pin on the PCB.

14

VBUF

Output of the LDO Reference Buffer. Connect a 0.1 µF ceramic capacitor between this pin and VFB2N.

15

AGND2

LDO Dedicated Analog Ground.

16

VREG_LDO

Internal Regulator Output for the LDO. Connect a 1 µF ceramic decoupling capacitor between this pin and

AGND2. Do not use this pin to power external devices.

17

VSET2

LDO Regulator Output Voltage Configuration Input.

18

REFOUT

Internal Reference Output Required for Driving the External Resistor Dividers for VSET1 and VSET2. Connect a

0.22 µF ceramic capacitor between this pin and AGND2.

19

VSET1

Buck Regulator Output Voltage Configuration Input. Connect this pin to VREG to enable adaptive headroom

control.

20

PWRGD

Power-Good Digital Output (Open-Drain NFET Pull-Down Driver).

21

COMP1

Buck Regulator External Compensation Pin.

22

RT

Resistor Adjustable Frequency Programming Input.

23

VREG

Internal Regulator Output. Connect a 1 µF ceramic decoupling capacitor between this pin and AGND1. Do not

use this pin to power external devices.

24

AGND1

Analog Ground.

25

PVINSYS

System Power Supply for the ADP5003. Connect a 10 µF ceramic capacitor between this pin and AGND1.

26, 27

PVIN1

Buck Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and PGND1.

28 to 30

SW1

Buck Regulator Switching Output.

EPAD

Exposed Thermal Pad. Connect the exposed thermal pad to AGND1.