数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ADP5003ACPZ-R7 数据表(PDF) 4 Page - Analog Devices

部件名 ADP5003ACPZ-R7
功能描述  Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO
PDF  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5003ACPZ-R7 数据表(HTML) 4 Page - Analog Devices

  ADP5003ACPZ-R7 Datasheet HTML 1Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 2Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 3Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 4Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 5Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 6Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 7Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 8Page - Analog Devices ADP5003ACPZ-R7 Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 31 page
background image
ADP5003
Data Sheet
Rev. A | Page 4 of 31
SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for
typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Min Typ Max Unit Test Conditions/Comments
INPUT VOLTAGE RANGE
VPVIN1, VPVINSYS 4.2
15
V
VPVIN2
0.65
5
V
THERMAL SHUTDOWN
Threshold
TSD
155
°C
TJ rising
Hysteresis
TSD-HYS
15
°C
SYNC INPUT
Input Logic
High
VIH
1.1
V
Low
VIL
0.4
V
Input Leakage Current
VI-LEAKAGE
1
µA
ADAPTIVE MODE INPUT (VSET1)
Input Rising Threshold
VADPR
2.5
V
Input Hysteresis
VADPH
16
mV
PRECISION ENABLING
High Level Threshold
VTH_H
1.125 1.15 1.175 V
Low Level Threshold
VTH_L
1.025 1.05 1.075 V
Shutdown Mode
VTH_S
0.4
V
EN1, EN2 Pull-Down Resistance
RENPD
1.5
INPUT CURRENT
Both Channels Enabled
ISTBY-NOSW
0.5 1
mA No load, not switching
Both Channels Disabled
ISHUTDOWN
5
10
µA
TJ = −40°C to +125°C
REFOUT CHARACTERISTICS
Output Voltage
VREFOUT
2.0
V
Accuracy
−0.5
+0.5 %
VREG AND VREG_LDO CHARACTERISTICS
Output Voltage
VREG, VREG_LDO
5
V
Accuracy
−2
+2
%
Current Limit1
10
mA
POWER-GOOD PIN (PWRGD)
Power Good Threshold
PWRGDF
80
85
90
%
Applies to VOUT1 and VFB2P to VFB2N
Hysteresis
PWRGDFH
2.5
%
Output Voltage Level
VOL
25
50
mV PWRGD pin sink current = 1 mA
Deglitch Time
tPWRGDD
60
µs
PVINSYS UNDERVOLTAGE LOCKOUT (UVLO)
Input Voltage
Rising
UVLOPVINSYSRISE
4.2
V
Falling
UVLOPVINSYSFALL 3.9
V
1
Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com