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STM32WLE4JC 数据表(PDF) 115 Page - STMicroelectronics |
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STM32WLE4JC 数据表(HTML) 115 Page - STMicroelectronics |
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115 / 146 page  DS13105 Rev 9 115/146 STM32WLE5/E4xx Electrical characteristics 133 tLATR Trigger conversion latency CKMODE = 00 2 - 3 1/fADC CKMODE = 01 6.5 1/fPCLK CKMODE = 10 12.5 CKMODE = 11 3.5 ts Sampling time fADC = 35 MHz 0.043 - 4.59 µs -1.5 - 160.5 1/fADC tADCVREG_STUP ADC voltage regulator start-up time -- - 20 µs tCONV Total conversion time (including sampling time) fADC = 35 MHz Resolution = 12 bits 0.40 - 4.95 µs Resolution = 12 bits ts + 12.5 cycles for successive approximation = 14 to 173 1/fADC tIDLE Laps of time allowed between two conversions without rearm -- - 100 µs IDDA(ADC) ADC consumption from VDDA fs = 2.5 Msps - 410 - µA fs = 1 Msps - 164 - fs = 10 ksps - 17 - IDDV(ADC) ADC consumption from VREF+ single ended mode fs = 2.5 Msps - 65 - µA fs = 1 Msps - 26 - fs = 10 ksps - 0.26 - 1. Guaranteed by design 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. Table 77. ADC characteristics(1) (continued) Symbol Parameter Conditions(2) Min Typ Max Unit Table 78. Maximum ADC RAIN values Resolution Sampling cycle at 35 MHz (ns) Sampling time at 35 MHz (ns) Max. RAIN(1)(2)(Ω) 12 bits 1.5(3) 43 50 3.5 100 680 7.5 214 2200 12.5 357 4700 19.5 557 8200 39.5 1129 15000 79.5 2271 33000 160.5 4586 50000 |
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