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STM32WLE4JC 数据表(PDF) 129 Page - STMicroelectronics |
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STM32WLE4JC 数据表(HTML) 129 Page - STMicroelectronics |
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129 / 146 page  DS13105 Rev 9 129/146 STM32WLE5/E4xx Electrical characteristics 133 All I2C SDA and SCL I/Os embed an analog filter (refer to the table below for its characteristics). USART characteristics Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 25: General operating conditions, with the following configuration: • OSPEEDRy[1:0] set to 10 (output speed) • capacitive load C = 30 pF • measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART). Table 90. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 100(3) ns 1. Guaranteed by characterization. 2. Spikes with widths below tAF(min) filtered. 3. Spikes with widths above tAF(max) not filtered. Table 91. USART characteristics Symbol Parameter Conditions Min Typ Max Unit fCK USART clock frequency Master mode - - 6 MHz Slave mode - - 16 tsu(NSS) NSS setup time Slave mode tker + 5 - - ns th(NSS) NSS hold time Slave mode 2 - - tw(CKH) CK high time Master mode 1 / fCK / 2 - 1 1 / fCK / 2 1 / fCK / 2 + 1 tw(CKL) CK low time tsu(RX) Data input setup time Master mode 22 - - Slave mode 3 - - th(RX) Data input hold time Master mode 0 - - Slave mode 1 - - tv(TX) Data output valid time Master mode - 13 22 Slave mode - 0.5 1 th(TX) Data output hold time Master mode 10 - - Slave mode 0 - - |
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