STM32WLE4JC datasheet(131/146 Pages) STMICROELECTRONICS

部件名	STM32WLE4JC

功能描述	Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM

PDF	146 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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131 / 146 page

DS13105 Rev 9

131/146

STM32WLE5/E4xx

Electrical characteristics

133

Figure 27. SPI timing diagram - Slave mode and CPHA = 0

tv(SO)

Data output valid time

Slave mode, 2.7 < VDD < 3.6 V

Range 1

13.5

Slave mode, 2.7 < VDD < 3.6 V

Range 2

-17

Slave mode, 1.8 < VDD < 3.6 V

Range 1

-10

Slave mode, 1.8 < VDD < 3.6 V

Range 2

-17

tv(MO)

Master mode (after enable edge)

1.5

th(SO)

Data output hold time

Slave mode (after enable edge)

th(MO)

Master mode (after enable edge)

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), that has to fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50 %.

Table 92. SPI characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

(SI)

MSB IN

BIT1 IN

LSB IN

BIT6 OUT

MSB OUT

LSB OUT

NSS input

MOSI

INPUT

MISO

OUTPUT

(SI)

STM32WLE4JC 数据表(PDF) 131 Page - STMicroelectronics

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