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STM32WLE4JC 数据表(PDF) 139 Page - STMicroelectronics |
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STM32WLE4JC 数据表(HTML) 139 Page - STMicroelectronics |
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139 / 146 page ![]() DS13105 Rev 9 139/146 STM32WLE5/E4xx Package information 140 Device marking for UFBGA73 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 35. UFBGA73 marking example (package top view) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. Table 97. UFBGA recommended PCB design rules (0.5 mm pitch BGA) Dimension Recommended values Pitch 0.5 mm Dpad 0.230 mm Dsm 0.330 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm Ball diameter 0.280 mm MSv64357V1 Date code Product identification (1) Y WW WLE5J8I6 Revision code R Pin 1 identifier |
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