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LSM6DSOX 数据表(PDF) 53 Page - STMicroelectronics |
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LSM6DSOX 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 199 page  9.10 COUNTER_BDR_REG1 (0Bh) Counter batch data rate register 1 (r/w) Table 40. COUNTER_BDR_REG1 register dataready_ pulsed RST_COUNT ER_BDR TRIG_COUN TER_BDR 0 0 CNT_ BDR_TH_10 CNT_ BDR_TH_9 CNT_ BDR_TH_8 Table 41. COUNTER_BDR_REG1 register description dataready_pulsed Enables pulsed data-ready mode (0: Data-ready latched mode (returns to 0 only after an interface reading) (default); 1: Data-ready pulsed mode (the data ready pulses are 75 µs long) RST_COUNTER_BDR Resets the internal counter of batching events for a single sensor. This bit is automatically reset to zero if it was set to ‘1’. TRIG_COUNTER_BDR Selects the trigger for the internal counter of batching events between XL and gyro. (0: XL batching event; 1: GYRO batching event) CNT_BDR_TH_[10:8] In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’. 9.11 COUNTER_BDR_REG2 (0Ch) Counter batch data rate register 2 (r/w) Table 42. COUNTER_BDR_REG2 register CNT_ BDR_TH_7 CNT_ BDR_TH_6 CNT_ BDR_TH_5 CNT_ BDR_TH_4 CNT_ BDR_TH_3 CNT_ BDR_TH_2 CNT_ BDR_TH_1 CNT_ BDR_TH_0 Table 43. COUNTER_BDR_REG2 register description CNT_BDR_TH_[7:0] In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’. LSM6DSOX COUNTER_BDR_REG1 (0Bh) DS12814 - Rev 3 page 53/199 |
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