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LSM6DSOX 数据表(PDF) 143 Page - STMicroelectronics |
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LSM6DSOX 数据表(HTML) 143 Page - STMicroelectronics |
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143 / 199 page  13.40 EMB_FUNC_ODR_CFG_B (5Fh) Finite State Machine output data rate configuration register (r/w). Table 319. EMB_FUNC_ODR_CFG_B register 0(1) 1(2) 0(1) FSM_ODR1 FSM_ODR0 0(1) 1(2) 1(2) 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device. Table 320. EMB_FUNC_ODR_CFG_B register description FSM_ODR[1:0] Finite State Machine ODR configuration: (00: 12.5 Hz; 01: 26 Hz (default); 10: 52 Hz; 11: 104 Hz) 13.41 EMB_FUNC_ODR_CFG_C (60h) Machine Learning Core output data rate configuration register (r/w). Table 321. EMB_FUNC_ODR_CFG_C register 0(1) 0(1) MLC_ODR1 MLC_ODR0 0(1) 1(2) 0(1) 1(2) 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device. Table 322. EMB_FUNC_ODR_CFG_C register description MLC_ODR[1:0] Machine Learning Core ODR configuration: (00: 12.5 Hz; 01: 26 Hz (default); 10: 52 Hz; 11: 104 Hz) LSM6DSOX EMB_FUNC_ODR_CFG_B (5Fh) DS12814 - Rev 3 page 143/199 |
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