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EFP01 数据表(PDF) 92 Page - Silicon Laboratories

部件名 EFP01
功能描述  EFP01 Energy Friendly PMIC Family
PDF  158 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EFP01 数据表(HTML) 92 Page - Silicon Laboratories

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6.2 Register Description
6.2.1 STATUS_G
Offset
Bit Position
0x00
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
Name
Table 6.1. STATUS_G
Bit
Name
Reset
Access
Description
7
VDD_LOW
0
read-write
Status flag indicating VDDB (or VDDA if
CC_MODE.SC_MODE=1) has fallen below threshhold
programmed in ADC_LIMITS.ADC_V_LIM since last clear.
This flag requires ADC_CC_CTRL.ADC_INTERVAL be
set to a non-zero value to ensure automatic periodic ADC
readings are taken.
Note this flag is masked by default - set corresponding bit
in the STATUS_GM register to unmask.
Can be cleared by writing a "1".
6
CCC_ISDONE
0
read-write
Status flag indicating coloumb counter calibration has
completed since last clear.
Note this flag is masked by default - set corresponding bit
in the STATUS_GM register to unmask.
Can be cleared by writing a "1".
5
CC_FULL
0
read-write
Status flag indicating any coloumb counter is over its pro-
grammed threshold (set by CC_CTRL>CC_THRSH) since
last clear.
Note this flag is masked by default - set corresponding bit
in the STATUS_GM register to unmask.
Can be cleared by writing a "1".
4
VOLT_FAULT
0
read-write
Status flag indicating any unmasked assertion of any flag
in the STATUS_V register. To minimize firmware over-
head, the VOLT_FAULT flag allows firmware to simply
read a single status register (STATUS_G) on an IRQ
event. Firmware would only need to read the STATUS_V
register after determing the STATUS_G.VOLT_FAULT
was set.
Note this flag is masked by default - set corresponding bit
in the STATUS_GM register to unmask.
Can be cleared by writing a "1".
EFP01 Energy Friendly PMIC Family Data Sheet
Register Definitions
silabs.com | Building a more connected world.
Rev. 1.3 | 92



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