EFP01 datasheet(23/158 Pages) SILABS

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3.3.1.2 Direct Mode Control

In direct mode, the internal pull-ups on the I2C_SDA and I2C_SCL pins are disabled, and the pins become high-impedance inputs that

the host processor can drive to quickly change energy modes.

Once enabled by setting the EM_DIRECTEN bit in the EM_CRSREG_CTRl register, direct mode allows the energy mode to be selec-

ted by driving the I2C_SDA and I2C_SCL pins according to Table 3.9 Direct Mode Energy Mode States on page 23. When I2C_SCL

and I2C_SDA enter the I2C Start Condition, direct mode is automatically disabled, and the EFP01 optionally enters EM0 if

FORCE_EM0 = 1 in the EM_CRSREG_CTRL register.

Note: Use of Direct Mode is not recommended unless the host processor has dedicated hardware support for EFP01 (e.g.,

EFR32xG22 and later devices). Although Direct Mode state control can be bit-banged, there can be some undesireable side effects.

For example, if the host processor receives a system reset (hard or soft) while in the Direct Mode EM0 or EM2 state, the host's I2C

outputs can be disabled and can float to logic low levels (because the EFP01's internal pull-ups are disabled in Direct Mode). Because

I2C_SCL = I2C_SDA = 0 is recognized by EFP01 as the EM4 state in Direct Mode, EFP01 disables its DCDC converters and LDO

outputs and enters EM4 where it can only supply ~100 μA. This low current output is insufficient for a host processor to boot, resulting

in an unusable state from which recovery is not possible without disconnecting and then reconnecting the power supply.

Note: Direct Mode is primarily intended for applications where the EFP01 is the only device on the I2C bus; other I2C devices may not

tolerate the non-standard I2C states used by Direct Mode.

Table 3.9. Direct Mode Energy Mode States

Direct Mode State

I2C_SCL Level

I2C_SDA Level

Allowed State Transitions

EM0

• EM21

• I2C Start Condition

EM2

• EM0

• EM4

EM4

• EM21

I2C Start Condition

• EM02

Note:

1. Direct mode transitions between EM0 and EM4 are not allowed. The system must briefly go through the EM2 state on EM4 exit or

entrance.

2. If the FORCE_EM0 bit in the EM_CRSREG_CTRL register is set, the internal device state will be set to EM0 automatically when-

ever the I2C start condition appears.

3.3.2 EM0

The EFP01 defaults to EM0 out of reset. In EM0, all features are enabled, and the maximum output current can be supported on any

enabled DCDC converters.

3.3.3 EM2

Functionally, EM2 is very similar to EM0, with the proviso that in EM2 bias currents are reduced for improved efficiency at the expense

of maximum supported output current.

DCDC A and DCDC B have independent peak current configuration bit fields for EM2 (in BB_IPK_EM2 and BK_IPK_EM2, respective-

ly). In addition, the VOB output target voltage has its own independent configuration in EM2 (VOB_EM2_V).

DCDC B has an independent result register for storing the Coulomb counter result in EM2 (CCB2_MSBY/LSBY). However, DCDC A

shares one set of registers for Coulomb counting in both EM0 and EM2. Because of this, DCDC A must should use the same peak

current setting in both EM0 and EM2 in order for the Coulomb count to be accurate.

EFP01 Energy Friendly PMIC Family Data Sheet

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