EFP01 datasheet(24/158 Pages) SILABS

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3.3.4 EM4

In EM4, the EFP01 disables all enabled DCDCs and LDOs, and enables any desired coarse regulators (i.e., those with their

CRSREG_EN_x bits set in the EM_CRSREG_CTRL register). ADC voltage and temperature measurements are disabled in EM4. Cou-

lomb counting is not supported in EM4.

While in EM4, the EFP01's registers can be read or written via I2C transactions, but the EFP01 will not generate any IRQs in EM4.

Several device configurations have restrictions on EM4 operation:

• In Figure 4.4 Single-Cell Boost Configuration on page 33, EM4 is not supported at all.

• In Figure 4.6 Boost Bootstrap Configuration on page 35, EM4 is supported only when the supply voltage > 2.5V

Note: Unless the host processor has dedicated EM4 hardware support for 3.3.1.2 Direct Mode Control, EM4 should not be used. Once

the EFP01 is in EM4, it is only able to source 100 μA per output, which may not be sufficient to power the host while it exits EM4 and

sends the necessary I2C command to place the EFP01 in EM2 or EM0. Dedicated EFP01 EM4 hardware support is available on

EFR32xG22 and later devices.

3.4 Measurement

3.4.1 Coulomb Counter

Note:

Refer to AN1188: EFP01 Coulomb Counting for a more detailed discussion of the Coulomb counter and example code.

The EFP01 has an integrated Coulomb counter that can losslessly measure the charge drawn from the battery for each DCDC and

LDO.

Before normal operation can begin, the Coulomb counter must go through a calibration phase. Periodically, recalibration may be neces-

sary due to changes in operating conditions (e.g., battery voltage or operating temperature).

3.4.1.1 Calibration

Overview

During calibration, a known internal current load is applied to the selected output, and the device counts the number of 10 MHz clock

cycles required for a fixed number of pulse-frequency modulation (PFM) pulses to occur. The CC_CAL register CCL_SEL,

CC_CAL_NREQ, and CCL_LVL fields respectively determine the output used (VOA, VOB, or VOC), the number of PFM pulses to

count, and the current load applied to the output. The CCC_MSBY and CCC_LSBY registers are retasked during calibration to store the

resulting number of 10 MHz clock cycles counted (note that only the CCC_MSBY and CCC_LSBY registers are used regardless of

which output is being calibrated). Based on these results, the charge-per-pulse (CPP) can be determined.

After configuration, calibration is initiated by setting the CC_CAL_STRT bit in the CMD register. If enabled, the Coulomb counter should

be disabled prior to calibration by setting writing a 0 to the CC_EN bit in the CC_CTRL register.

For accurate calibration, any devices or loads powered by the EFP01's outputs are expected to be in a stable, steady-state of operation

during this calibration phase. In practice, occasional recalibration of the Coulomb counter is expected, particularly when either the input

voltage or the temperature has changed significantly.

EFP01 Energy Friendly PMIC Family Data Sheet

System Overview

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