EFP01 datasheet(25/158 Pages) SILABS

25 / 158 page

Factors Affecting the Charge-Per-Pulse

The charge-per-pulse (CPP) may vary depending on the operating mode of the converter. For example, if DCDC B is configured in

buck with LDO mode (i.e., the converter automatically switches between buck and LDO modes depending on input voltage), the CPP

when the converter is in buck can differ from the CPP when the converter is operating in LDO mode. For this reason, it may be neces-

sary to calibrate a given DCDC converter in each of its expected operating modes. Thus if DCDC B is in buck with LDO mode, and the

battery voltage is sufficiently close to the output voltage such that the converter may switch to LDO mode, calibration should be per-

formed on DCDC B once in buck mode and again in LDO mode.

The current DCDC operating modes of DCDC A and DCDC B are reported by the CCA_MODE and CCB_MODE fields of the

CC_MODE register, respectively. For calibration purposes, the operating modes can be temporarily forced using the BB_MODE and

BK_MODE fields in the BB_CTRL3 and BK_CTRL1 registers for DCDC A and DCDC B, respectively. Host firmware is expected to

maintain a CPP for each operating mode of the converter.

In addition, the energy mode can affect the charge-per-pulse. The VOB output has independent result registers for EM0 and EM2, and

will need to be calibrated in each energy mode. The VOA and VOC outputs each have only a single result register pair used in both

EM0 and EM2. If Coulomb Counting is use with VOA, the BB_IPK and BB_IPK_EM2 peak current values are expected to be the same

to ensure an accurate count on VOA regardless of energy mode.

3.4.1.2 Recalibration

In addition, certain changes in external conditions may affect the charge-per-pulse. The below list contains conditions that may necessi-

tate a recalibration event:

• Significant change in input supply voltage

• Significant change in temperature

3.4.1.3 Operation

Note:

Refer to AN1188: EFP01 Coulomb Counting for a more detailed discussion of the Coulomb counter and example code.

PFM pulse counts for the VOA, VOB (separately for EM0 and EM2), and VOC outputs are stored in the CCA_MSBY/CCA_LSBY

(VOA), CCB0_MSBY/CCB_LSBY (VOB in EM0), CCB2_MSBY/CCB2_LSBY (VOB in EM2), and CCC_MSBY/CCC_LSBY (VOC) most

significant/least significant byte register pairs, respectively, during normal operation.Note that when DCDC A is operating with LDO C in

parallel, the resulting counts will be split between the CCA result registers (when the DCDC A is powering the load) and the CCC result

registers (when LDO C is powering the load).

Prescaler

The actual value stored in a given Coulomb counter result register pair is scaled according to the CC_PRESCL field in the CC_CTRL

register. This setting applies globally such that the count in a given result register pair represents 2(16-2×CC_PRESCL) PFM pulses. Note

that the prescaler setting does not affect the CCC_MSBY/LSBY registers during calibration.

Enabling / Disabling

Start Coulomb counting by writing a 1 to the CC_EN bit in the CC_CTRL register; stop counting by writing a 0 to CC_EN.

Servicing

Once enabled, the Coulomb counter result registers will eventually overflow, so some amount of firmware maintenance is required. The

CC_THRSH field in the CC_CTRL register sets the desired threshold (50%, 62.5%, 75%, or 87%) for setting the STATUS_G register

CC_FULL flag. Note that the CC_FULL_UNMASK bit in the STATUS_GM register must be written to 1 so that an interrupt can be re-

quested when the CC_FULL flag is set. When firmware receives an interrupt, and discovers that CC_FULL is set, all relevant Coulomb

counter result registers should be read and added to local variable counts. Additionally,each converter's operating mode should be de-

termined (by reading the CCA_MODE or CCB_MODE field in the CC_MODE register for DCDC A or DCDC B, respectively) in order to

perform battery life calculations using the relevant CPP value. Clear the Coulomb counter result registers after reading them by writing

a 1 to the CC_CLR bit in the CMD register.

EFP01 Energy Friendly PMIC Family Data Sheet

System Overview

silabs.com | Building a more connected world.

Rev. 1.3 | 25

EFP01 数据表(PDF) 25 Page - Silicon Laboratories

EFP01 数据表(HTML) 25 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载