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3.6.2 Interrupt Output (IRQ)

The EFP01 has an open-drain Interrupt Output (IRQ) that can be used to notify the host processor. Out of reset, an internal pull-up will

be enabled on the IRQ pin - this pull-up will always remain enabled and cannot be disabled.

An IRQ will be generated whenever both of the following conditions are true:

• A status flag is set in either the STATUS_G or STATUS_V registers

• The flag's corresponding UNMASK bit in either the STATUS_GM or STATUS_VM registers is also set to one.

When an IRQ is generated, the IRQ pin will be driven low until any flags that are both unmasked and set are cleared.

By default, only the STATUS_GM.OTP_READ_UNMASK bit is set, which results in an IRQ whenever the OTP is read. Because the

OTP is read on every EFP01 power-up and/or reset, the host firmware can use this OTP_READ flag and resulting IRQ as an indication

that an unexpected reset condition has occurred on the EFP01, and that any post-startup configuration needs to be rewritten to its

registers.

3.7 System Protection

3.7.1 Under-voltage Lockout (UVLO)

When the VDDB voltage falls below the UVLO trip point (consult Electrical Specifications table for the typical value), the EFP01 auto-

matically transitions to an extremely low-power state to minimize power consumption. In this state, only the Power-On Reset (POR) is

enabled.

3.7.2 Power-on Reset (POR)

When the VDDB voltage rises above the Rising POR threshhold (consult Electrical Specifications table), the EFP01 automatically loads

its OTP programmed defaults into the corresponding registers, at which point any enabled converters will begin regulation. If the VDDB

voltage falls below the Falling POR threshhold, the EFP01 will go into reset and all outputs will be disabled.

3.7.3 Over-Voltage Protection

By default in EM0 and EM2 modes, each output has overvoltage protection enabled. When the output voltage on a specific converter is

more than ~180 mV higher than the programmed value, an internal ~2 mA load is enabled on the output until the overvoltage condition

clears. This feature can be disabled on the VOB output by setting the BK_CTRL0.BK_DIS_OV_PROT bit.

In OPNs where DCDC B is providing an output that must stay between 1.1 V to 1.2 V, the coarse regulator cannot be enabled in EM4

(as the coarse LDO output can be much higher than 1.2 V). To ensure the supply voltage in EM4 does not increase beyond an accepta-

ble level due to leakage, a simple voltage clamp can be enabled on the VOB output by setting the BK_CTRL0.CLAMPB bit.

EFP01 Energy Friendly PMIC Family Data Sheet

System Overview

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EFP01 数据表(PDF) 28 Page - Silicon Laboratories