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3.2.3.5 LDO Startup

In some configurations, the LDO input supply (i.e., the VDDB pin) is powered from the VOA output. The VOA output may see momenta-

ry voltage droops when the LDO is enabled due to instantaneous current required to charge the 10µF capacitors on the LDO outputs.

To avoid this, the current limit can be enabled before the LDO is enabled and then disabled after the LDO output is stable. Consult

3.2.3.4 LDO Current Limiting for more information.

3.2.3.6 DCDC to LDO Transition

When DCDC A or B is operating with a LDO in parallel, at some point the VDDB input supply voltage approaches the LDO output volt-

age causing the controller to switch from DCDC mode to LDO mode. The dropout voltage (VDDB-VOB for LDO B or VDDB-VOC for

LDO C) at which this transition from DCDC to LDO occurs is controlled by the BK_LDO_THRESH bit field in the BK_CTRL2 register for

DCDC B / LDO B, and by the NTM_LDO_THRSH bit field in the BB_CTRL3 register for DCDC A / LDO C.

3.2.3.7 Bypass Mode

Both LDO B and LDO C support a bypass mode, in which the VDDB pin input voltage is shorted directly to the corresponding output pin

(VOB and VOC, respectively). By default, both LDOs automatically enter bypass mode when the input supply voltage at VDDB drops

too low to maintain regulation accuracy. This behavior can be disabled for both LDOs by setting the LDO_NO_AUTO_BYP bit in the

LDOB_CTRL register.

In addition, both LDO B and LDO C can be forced into bypass mode by setting the BYP bit in the LDOB_CTRL and LDOC_CTRL regis-

ters, respectively. When forcing bypass mode, care must be taken to ensure that any loads attached to the LDO output pins (VOB and

VOC) are tolerant of the VDDB pin input voltage.

3.2.4 Coarse Regulators

Each EFP01 output (VOA, VOB, VOC) has its own coarse regulator in parallel for use in EM4. The coarse regulators have very low

quiescent current draw but poor output regulation — the outputs may range from 1.69V to 3.4V — and can only support very light loads

(100μA).

The coarse regulator for each output can be enabled by setting the corresponding CRSREG_EN_x bit in the EM_CRSREG_CTRL reg-

ister. If the CRSREG_BYP bit is set, any enabled coarse regulator's output (VOA, VOB, or VOC pin) is shorted to its input (the VDDB

pin).

For certain OPNs (EFP0102/04/07/08/10) the maximum VOB output is limited to 1.26V, which is incompatible with both the coarse reg-

ulator and the bypass mode. For this reason, the VOB coarse regulator and VOB coarse regulator bypass features are disabled on

these OPNs.

EFP01 Energy Friendly PMIC Family Data Sheet

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EFP01 数据表(PDF) 21 Page - Silicon Laboratories