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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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EFP01 数据表(PDF) 93 Page - Silicon Laboratories |
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EFP01 数据表(HTML) 93 Page - Silicon Laboratories |
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93 / 158 page  Bit Name Reset Access Description 3 TEMP_FAULT 0 read-write Status flag indicating an over temperature condition has occurred since last clear. Temperature threshold is set by ADC_LIMITS.ADC_T_LIM. This flag requires ADC_CC_CTRL.ADC_INTERVAL be set to a non-zero value to ensure automatic periodic ADC readings are tak- en. Note this flag is masked by default - set corresponding bit in the STATUS_GM register to unmask. Can be cleared by writing a "1". 2 I2C_FAULT 0 read-write Status flag indicating an I2C fault has occurred since last clear. Note this flag is masked by default - set corresponding bit in the STATUS_GM register to unmask. Can be cleared by writing a "1". 1 OTP_CRC_FAULT 0 read-write Status flag indicating an OTP CRC violation has occurred since last clear. Note this flag is masked by default - set corresponding bit in the STATUS_GM register to unmask. Can be cleared by writing a "1". 0 OTP_READ 0 read-write Status flag indicating that OTP was read since last clear. This flag is expected to be set everytime the EFP01 is powered up, and should be cleared at power-up. It is recommended to keep this flag unmasked always to ensure that any EFP01 reset will result in an IRQ to the host MCU, allowing the host MCU to reinitialize any EFP01 registers. Note this flag is unmasked by default - therefore, every power-up and reset deassertion (which causes an OTP read), results in an unmasked flag and the IRQ pin asser- tion. Can be cleared by writing a "1". EFP01 Energy Friendly PMIC Family Data Sheet Register Definitions silabs.com | Building a more connected world. Rev. 1.3 | 93 |
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