R5F104FCAFP datasheet(46/207 Pages) RENESAS

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RL78/G13

1. OUTLINE

R01DS0131EJ0350 Rev.3.50

46 of 200

Jun 30, 2020

[40-pin, 44-pin, 48-pin, 52-pin, 64-pin products]

Caution

This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set

to 00H.

(1/2)

Item

40-pin

44-pin

48-pin

52-pin

64-pin

Code flash memory (KB)

16 to 192

16 to 512

32 to 512

Data flash memory (KB)

4 to 8

–

4 to 8

–

4 to 8

–

4 to 8

–

4 to 8

–

RAM (KB)

2 to 16Note1

2 to 32Note1

Address space

1 MB

Main system

clock

High-speed system

clock

X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)

HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),

HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),

LS (Low-speed main) mode:

1 to 8 MHz (VDD = 1.8 to 5.5 V),

LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)

High-speed on-chip

oscillator

HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),

HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),

LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),

LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)

Subsystem clock

XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)

32.768 kHz

Low-speed on-chip oscillator

15 kHz (TYP.)

General-purpose registers

(8-bit register × 8) × 4 banks

Minimum instruction execution time

0.03125 µs (High-speed on-chip oscillator: fIH = 32 MHz operation)

0.05 µs (High-speed system clock: fMX = 20 MHz operation)

30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation)

Instruction set

● Data transfer (8/16 bits)

● Adder and subtractor/logical operation (8/16 bits)

● Multiplication (8 bits × 8 bits)

● Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.

I/O port

Total

CMOS I/O

(N-ch O.D. I/O

[VDD withstand

voltage]: 10)

(N-ch O.D. I/O

[VDD withstand

voltage]: 10)

(N-ch O.D. I/O

[VDD withstand

voltage]: 11)

(N-ch O.D. I/O

[VDD withstand

voltage]: 13)

(N-ch O.D. I/O

[VDD withstand

voltage]: 15)

CMOS input

CMOS output

–

N-ch O.D. I/O

(withstand voltage: 6 V)

Timer

16-bit timer

8 channels

Watchdog timer

1 channel

Real-time clock (RTC)

1 channel

12-bit interval timer (IT)

1 channel

Timer output

4 channels (PWM

outputs: 3 Note2),

8 channels (PWM

outputs: 7 Note2)Note3

5 channels (PWM outputs: 4 Note 2),

8 channels (PWM outputs: 7 Note 2) Note 3

8 channels (PWM

outputs: 7 Note 2)

RTC output

1 channel

● 1 Hz (subsystem clock: fSUB = 32.768 kHz)

Notes 1.

The flash library uses RAM in self-programming and rewriting of the data flash memory.

The target products and start address of the RAM areas used by the flash library are shown below.

R5F100xD, R5F101xD (x = E to G, J, L): Start address FF300H

R5F100xE, R5F101xE (x = E to G, J, L):

Start address FEF00H

R5F100xJ, R5F101xJ (x = F, G, J, L):

Start address FAF00H

R5F100xL, R5F101xL (x = F, G, J, L):

Start address F7F00H

For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for

RL78 Family (R20UT2944).

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