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R5F104FCAFP 数据表(PDF) 26 Page - Renesas Technology Corp

部件名 R5F104FCAFP
功能描述  True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz
PDF  207 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F104FCAFP 数据表(HTML) 26 Page - Renesas Technology Corp

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RL78/G13
1. OUTLINE
R01DS0131EJ0350 Rev.3.50
26 of 200
Jun 30, 2020
1.3.13 100-pin products
● 100-pin plastic LFQFP (14 × 14 mm, 0.5-mm pitch)
RL78/G13
(Top View)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102/TI06/TO06
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P145/TI07/TO07
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TxD1)
P81/(SI10)/(RxD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVSS1
P05
P06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RxD2)
P77/KR7/INTP11/(TxD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
P62/SCLA1
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Cautions 1. Make EVSS0 and EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is no less than EVDD0 and EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and
connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13 User’s Manual.



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